The present invention relates in general to phase lock loops and, more particularly, to a high frequency voltage controlled oscillator with digital controlled loads.
A conventional phase lock loop (PLL) generally includes a phase detector for monitoring a phase difference between an input signal and an output signal of a voltage controlled oscillator (VCO). The phase detector generates an up control signal and a down control signal for a charge pump to charge and discharge a loop filter at a loop node at the input of the VCO. The loop voltage developed across the loop filter determines the output frequency of the VCO. The up and down control signals driving the charge pump set the proper loop filter voltage at the input of the VCO to maintain a predetermined phase relationship between the signals applied to the phase detector.
PLLs are widely used in data communications, local area networks in computer applications, microprocessors and data storage applications to control data transfers. PLLs are often implemented with Complementary Metal Oxide Semiconductor (CMOS) technology to provide low cost and low power operation allowing a system designer to extend the tracking range and frequency-aided acquisition. As the operating frequency of PLLs continue to increase to meet the demand for higher communication data rates, the system designer must deal with problems of temperature and manufacturing process variation affecting the operation of the PLL. The VCO is a primary temperature and process sensitive component affecting high frequency PLL operation. Ideally, the VCO should operate at a known frequency given a loop node voltage. However, the actual operating speed of a VCO, given a loop node voltage, is often uncertain.
A typical maximum operating frequency for a conventional VCO is 100 MHz under worst case processing. It is desirable for the VCO to operate at least 200 MHz with the loop node voltage at its maximum (V.sub.DD), even under worst case processing and high temperature conditions based on operating environment and wafer characteristics. However, under the best case temperature and processing conditions, the same VCO design may operate at a much higher frequency, say 860 MHz, with the same loop node voltage V.sub.DD. In fact, the entire frequency-gain curve (MHz/volt) of the VCO operation is affected by temperature and processing conditions. For example, the VCO frequency gain under worst case processing may be 17 MHz/volt at 200 MHz, while under best case processing conditions, the VCO frequency gain is 365 MHz/volt. Thus, the uncertainty in VCO output frequency as a function of temperature and process parameters given a loop node voltage, effects accuracy, stability, jitter and tuning range of the PLL.
Hence, a need exists for a high frequency VCO to operate at a known frequency given a loop node voltage.